One of conventional design technologies for testability, which facilitate tests on semiconductor integrated circuits (for example, LSI (Large Scale Integrated-circuit)), is a technology called BIST (Built-In Self Test). BIST is a technology that embeds in a semiconductor chip a self-diagnostic test circuit that generates and outputs a test pattern and performs a comparison of test results.
BIST includes a logic BIST in which logic circuits in semiconductor integrated circuits are under test and a RAM-BIST (also referred to as “memory BIST” or “RBIST”) in which RAM (Random Access Memory) blocks are under test.
The RAM-BIST is a technique that embeds in a chip a RAM-BIST circuit, which includes a pattern generating circuit for generating test patterns in accordance with a predetermined program, an address generating circuit for generating a storage address for data to be read from or written to upon testing; and a result comparing circuit for comparing data read from a RAM with an expected value, and the RAM-BIST is widely used in the design of LSI circuits with a cache memory.
Clock frequencies of currently-available chips are now of the order of a GHz. This makes it difficult for a RAM with a large number of word lines to operate in one cycle (i.e., the cycle of a clock signal). For this reason, a 1τ-RAM with a small number of words that operates in one cycle and a 2τ-RAM with a large number of words that operates in two cycles are mounted on a chip.
However, to generate test patterns for their respective 1τ-RAM and the 2τ-RAM by the same method as that of a conventional RAM-BIST circuit, it is necessary to prepare, as a program used in the pattern generating circuit, a program being able to generate two patterns: a pattern for causing a RAM to operate in one cycle and a pattern for causing a RAM to operate in two cycles. In this case, the area for storing the program requires double the number of words compared with that required by a conventional RAM-BIST circuit, resulting in an increase in the scale of the RAM-BIST circuit.
[Patent Document] Japanese Laid-open Patent Publication No. 06-28896